1. Field of the Invention
The present invention relates to optoelectronic devices and, in particular, to a silicon-based integrated optoelectronic circuit chip having an avalanche photodetector and a method of making the chip using CMOS compatible processes.
2. Description of the Related Art
A number of difficulties have been encountered in the development of integrated solid-state photodetectors, i.e. photodetectors that are built or integrated on the same silicon wafer or chip as that of its associated electronic circuitry. Resolution of the problems requires the developer to optimize myriad parameters involving the properties of optical communication systems (e.g. operating wavelengths), fundamental optical properties of silicon (e.g. the band gap energy of Si and thus its wavelength absorption), and properties of other co-fabricated devices (e.g. P-type field effect transistor (PFET) or N-type field effect transistor (NFET)) which are to be simultaneously fabricated with the photodetector on the same chip. The problems are far more acute in the field of optical data communications because the speed and sensitivity of the photodetectors can significantly affect the performance of the communication systems.
It is known that for fast photodetection, photons should be collected rapidly. This is readily achieved by absorbing them in a region where the optically generated carriers (i.e. electrons and holes) can be collected by an electric field to form a photocurrent. Furthermore, it is known that the lowest cost, highest volume microelectronics process available is the Complementary Metal Oxide Silicon (CMOS) process, thus making it a desirable process for co-fabricating a photodetector. In CMOS, process depths are typically shallow (e.g. 3 microns or less), and get shallower as process line-widths shrink. Owing to the optical properties of silicon, the absorption depth for the most popular local area communications wavelengths (800-850 nm) exceeds this depth by a considerable margin. Therefore, a significant portion of the photogenerated carriers would be created outside any depletion region. As a result, a photocurrent is produced only when these photogenerated carriers diffuse into the depletion region. Since the diffusion process is driven by random motion of the carriers, it is a relatively slow transport mechanism, thereby rendering integrated silicon-based photodetectors made in CMOS process impractical for application in high-speed data communication systems.
Another problem with silicon-based integrated photodetectors is that their manufacturing process must be compatible with that of devices such, for example, as PFETs and NFETs which are co-fabricated on the same silicon chip. For example, one prior art technique produces a photodetector beneath a relatively thick stack of dielectric layers whose combined thickness cannot be controlled to the level required for anti-reflection coatings. As a result, such photodetectors have low sensitivity or responsivity, i.e. low gain, and their outputs suffer about 3 dB potential variability in sensitivity from the ideal value. To improve responsivity of these photodetectors, one must accordingly either overcoat the photodetectors with an optimizing film or remove all of the overlying dielectric layers and then directly apply an anti-reflection coating thereon. Such additional processing steps, however, undesirably increase the complexity and cost of fabrication.
Another known technique requires selective epitaxial growth and multiple growth runs to integrate photodetectors made of III-V compound materials. Still another approach requires the fabrication of III-V LED layers on a silicon substrate and thereafter uses the silicon substrate to create photodetectors. A problem with these approaches is that there exists large lattice mismatch between the III-V epitaxial layers and the silicon substrate; such a defect degrades the response of such photodetectors. Although acceptable for monitoring applications, such photodetectors do not meet the stringent requirements of optical data communication systems that operate at data rates of 200 Mbits per second or more.
There is accordingly a long felt need for a low-cost, fully-integrated photodetector that has low noise, can be operated at a low bit error rate, and exhibits high speed and high sensitivity.
An object of the present invention is to provide a low-cost integrated optoelectronic circuit chip having an avalanche photodetector that exhibits low-noise, high-speed response and high-sensitivity characteristics.
According to one aspect of the present invention, the inventive integrated avalanche photodetector (APD) is capable of being realized in concert with CMOS electronics, and can be fabricated in the same substrate using bulk CMOS-compatible processes. An advantage of such a photodetector is that it is inexpensive to manufacture and avoids the added complexity and parasitic electronic effects associated with packaging silicon-based receiver circuits with detectors made of different or separate materials.
According to another aspect of the invention, the integrated avalanche photodetector is fabricated together with PFETs and NFETs on the same silicon substrate.
According to still another aspect of the present invention, the integrated avalanche photodetector includes an isolating region for isolating its active regions from the photogenerated charge carriers from the silicon substrate.
An avalanche photodetector operates by a mechanism known as avalanche multiplication. The avalanche multiplication mechanism involves impact ionization of lattice atoms by charge carriers, i.e. electrons and/or holes, freed by the absorption of optical energy. These freed charge carriers, when they drift into a region having a sufficiently high electric field, are imparted with kinetic energy appropriate to initiate the avalanche multiplication process, which is a mechanism for breakdown in P-N junction diodes. The highly energetic charge carriers then collide with and ionize the other atoms in the lattice, to thereby free more charge carriers which in turn collide with many other atoms in the lattice to yield still more freed carriers. In this manner, an avalanche photodetector can detect a weak optical signal and yet output in response a much larger photogenerated current (i.e. photocurrent) within a very short time. Since the amplification of charge carriers is internal to the photodetector, the avalanche photodetector has low noise characteristics as compared to one that requires external amplifiers. Further explanation of the avalanche multiplication mechanism may be found at pp. 98-108 of S.M. Sze, xe2x80x9cPhysics of Semiconductor Devices,xe2x80x9d John Wiley and Sons (1981), which is incorporated herein in its entirety.
In a currently preferred embodiment, an integrated optoelectronic circuit chip for optical data communication systems includes at least one MOS transistor formed on a portion of a silicon substrate, and an avalanche photodetector (APD) formed on another portion of the silicon substrate. The chip includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is capable of being ionized by the incident optical signal to form freed charge carriers. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type, such that the light absorbing region and light responsive region form a P-N junction at the interface between the light absorbing region and light responsive region so that when the light absorbing region and the light responsive region are reverse biased to near the breakdown voltage, the freed charge carriers in the light absorbing region ionized by the incident optical signal are amplified by avalanche multiplication. The APD further includes a guard ring extending circumferentially along an edge of the light responsive region and configured for preventing premature breakdown of the APD.
The inventive method of fabricating an integrated optoelectronic circuit chip includes the steps of:
(a) providing a silicon substrate;
(b) forming at least one MOS field effect transistor on one portion of the silicon substrate using a CMOS compatible process; and
(c) forming an avalanche photodetector on another portion of the silicon substrate using the CMOS compatible process by:
(i) doping the another portion of the silicon substrate with a dopant of a first conductivity type so as to form a light absorbing region having a depth h1 and of the first conductivity type;
(ii) doping a portion of the light absorbing region with a dopant of a second conductivity type which is of opposite polarity to the first conductivity type to a depth h2 less than h1, so as to form a light responsive region of the second conductivity type and having a height h2, to thereby define a P-N junction at an interface between the light absorbing region and the light responsive region; and
(iii) forming a guard ring circumferentially along an edge of the light responsive region for preventing premature breakdown of the photodetector when the light absorbing region and the light responsive region are reverse biased to create avalanche multiplication conditions.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.